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Simulation Assignment
Number |
Description |
Due
Date |
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1 |
Read Chapters 1 and 2 of the Altera's MAX+plus II and the UP 1 Educational Board manual. As directed by your laboratory instructor, demonstrate schematic capture techniques, digital simulation of the Binary Counter design example, and the rapid prototyping of the design on an Altera UP 1 Educational Board which is present in the RPL Lab. |
Friday |
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2 |
Read Chapters 3 and 4 of the Altera's MAX+plus II and the UP 1 Educational Board manual and the handout on ModelSim VHDL Compiler and Simulator. As directed by your laboratory instructor, utilize basic VHDL design entry techniques on binary to hexadecimal converter example and utilize hybrid VHDL/schematic capture techniques hexadecimal counter design. Implement both designs on an Altera UP 1 Educational Board which is present in the RPL and demonstrate to your laboratory instructor. During this process, simulate the VHDL based hexadecimal converter design in the Altera MAX+plus II environment and on the ModelSim VHDL compiler/simulator. Add the VHDL clause after 10 ns to each section of the with/select statement in the b2h.vhd file. Recompile and simulate in both the Altera and ModelSim environments. Compare the outputs of both simulators, explain how do they differ? |
Friday |